The Custom Silicon War
The Custom-Silicon War – Google’s TPU, Amazon’s Trainium, and the End of the GPU Monopoly
For the better part of three years, the conventional wisdom on AI hardware was simple. If you wanted to train a frontier model, you bought Nvidia. The reasoning had two parts. The first was that Nvidia’s CUDA software stack was so far ahead of every alternative that no serious model could be trained on anything else. The second was that Nvidia’s hardware was the only accelerator for which you could reliably get volume. By 2023 the lead looked almost unbreakable, and the company’s market capitalisation briefly crossed three trillion dollars on the back of it.
That story is no longer the full story. As of 2026 every major hyperscaler ships its own AI accelerator at production scale. Google runs Gemini on its sixth-generation Tensor Processing Unit, called Trillium, with single clusters carrying over ninety exaflops of peak compute and more than one hundred thousand chips wired together. Amazon runs Anthropic’s Claude on a campus in Indiana built almost entirely around its second-generation Trainium chip, with the third generation coming on stream in late 2025 and a fourth already on the roadmap. Microsoft has its own Maia line, now in its second generation on a three-nanometre process, running the inference for OpenAI’s models, Microsoft 365 Copilot, and the rest of Microsoft’s internal AI services. Meta, which has the most idiosyncratic strategy of the four, runs hundreds of thousands of its MTIA chips for the ads-and-recommendation systems that pay its bills, with the next generation designed to take on general AI workloads and a partnership with Broadcom to ship more than a gigawatt of custom silicon across the rest of the decade.
The custom-silicon war is not new in origin. Google announced the first TPU in 2016 and quietly deployed it across its data centres for years before the broader AI industry noticed. What is new is the scale, the speed, and the sheer dollar value of the commitments now being made. Anthropic alone has contracts worth roughly half a trillion dollars in committed compute across AWS, Google, Microsoft, CoreWeave, SpaceX’s Colossus, Akamai, Fluidstack, and Nscale, spanning four separate silicon ecosystems. The shape of the frontier-AI industry in 2026 is not Nvidia plus a few curious experiments. It is a multi-polar compute market in which Nvidia is still the largest single supplier but is no longer the only serious option for anyone who matters.
This essay is an attempt to describe that new shape with some precision. We will walk through the four hyperscaler chip programmes one at a time, then look at the companies that design them on contract, then at Nvidia’s response, and finally at the part of the story that is least visible from the outside but most binding on the outcome: the physical limits of advanced packaging and high-bandwidth memory. By the end the picture should be clearer. The GPU monopoly did not collapse. It is being steadily surrounded.
The Nvidia problem
To understand why every hyperscaler now builds its own AI chip, you have to take the Nvidia position seriously first. Nvidia is not a struggling incumbent. The Hopper generation, led by the H100 and H200, was the dominant training and inference accelerator for the 2023 to 2025 model cycle. The Blackwell generation, led by the B100, B200, and the rack-scale GB200 NVL72 system, is now the default purchase for any organisation that wants a frontier-scale cluster and is not already vertically integrated. Nvidia holds an estimated sixty per cent of TSMC’s advanced-packaging capacity for 2026, roughly half a million wafers, more than any other single customer. Its NVLink interconnect, Spectrum-X Ethernet, Quantum InfiniBand switches, and BlueField DPUs together form a networking stack that no competitor has matched at scale. Its CUDA software library has roughly five million developers and tens of thousands of pre-optimised models. Replacing it is not a procurement decision. It is a multi-year, multi-billion-dollar engineering project.
And yet the hyperscalers are doing it. The reasons are practical and largely economic. The first is supply. Between late 2023 and mid-2025 lead times for H100 systems stretched out to between thirty-six and fifty-two weeks at peak, and even large customers were allocated rather than purchasing freely. When you cannot buy the chip you want at the price you want, designing your own starts to look less like hubris and more like insurance.
The second is unit economics. Anthropic’s published compute costs, broken down by analysts who read its IPO prospectus, show that the company’s annualised compute bill runs at roughly four billion dollars in 2026, against an estimated seven billion in revenue. The vast majority of that bill is paid to AWS, Google, and Microsoft for chips, networking, and data-centre space. Every percentage point of margin that can be recovered by owning more of the silicon stack drops directly to gross margin. Anthropic, like the other frontier labs, is now deeply unprofitable on a compute-cost-of-goods basis, and the difference between sixty-five per cent margin and seventy per cent margin on a four-billion-dollar cost base is a quarter of a billion dollars a year.
The third reason is workload fit. A general-purpose GPU is an awkward fit for some classes of AI workload. Ranking and recommendation systems, which dominate the inference traffic at Meta, ByteDance, and the Chinese internet platforms, are dominated by memory-bandwidth-bound operations on relatively small models. A chip designed for that workload can deliver substantially higher throughput per watt than a general-purpose GPU, even one as well-tuned as the H100. The same is true, in different ways, for inference on large language models at very high batch sizes, where memory bandwidth and KV-cache size matter more than raw floating-point throughput. Hyperscaler chips are not built to win benchmarks. They are built to win specific production workloads at acceptable cost.
The fourth reason is control. When you design your own chip, you decide what gets built, when it gets built, how it integrates with your data-centre power and cooling systems, and what its successor will look like. When you buy Nvidia, you take what Jensen Huang gives you. For a hyperscaler running tens of billions of dollars of capital expenditure per year, that loss of control is expensive even when the chip itself is excellent.
Google’s TPU – the longest war
Google’s Tensor Processing Unit predates the modern AI industry. The first generation shipped internally in 2016, and by the third generation, which Google called TPU v3, the chip was being used to train models that would not have been possible to train on the available GPUs at the time. Google spent roughly a decade iterating on the design before the rest of the industry took much notice. By the time the fifth-generation TPU v5p reached production in mid-2024, however, the chip had become the largest non-Nvidia training cluster in commercial operation, with pods of up to 8,960 chips wired together by Google’s proprietary Inter-Chip Interconnect.
The sixth generation, called Trillium and announced in May 2024, became generally available to Google Cloud customers in late 2025. Its headline numbers are striking. Each chip carries thirty-two gigabytes of HBM3e memory at roughly 1,600 gigabytes per second of bandwidth, the largest HBM configuration on any non-Nvidia accelerator shipping at the time. Peak compute per chip is roughly 4.7 times that of its predecessor TPU v5e, with energy efficiency improved by sixty-seven per cent. A Trillium pod scales to 256 chips at very high bandwidth, and Google’s Multislice technology lets multiple pods be wired together into clusters of tens of thousands of chips. The largest Trillium deployment, anchored by Google’s Jupiter data-centre fabric at thirteen petabits per second of bisectional bandwidth, carries more than 100,000 chips in a single network domain and delivers more than ninety exaflops of aggregate compute, four times the largest v5p cluster.
Google uses Trillium for its own Gemini training. The chips also became the basis of a series of large commercial deals in late 2025 and 2026, the largest of which is with Anthropic. In October 2025 Anthropic announced an agreement to use up to one million TPUs, with well over a gigawatt of capacity coming online across 2026. In April 2026 Google and Broadcom jointly agreed to provide Anthropic with an additional roughly five gigawatts of next-generation TPU capacity starting in 2027, with deliveries running through 2031. Taken together, Anthropic’s TPU commitments are now comparable in scale to its AWS Trainium commitments and run on a separate design and supply chain.
The point of Google’s long investment in TPUs is that the chips, the interconnect, the data-centre fabric, the compilers, the JAX software stack, and the model-training pipelines have been co-designed for ten years. That kind of vertical integration is what the other hyperscalers are trying to build. None of them are there yet, but several are getting closer.
Amazon’s Trainium – built for one customer
Amazon’s AI accelerator programme has a sharper commercial profile than Google’s. The chips come from Annapurna Labs, an Israeli chip-design company Amazon acquired in 2015, and they ship under the Trainium brand. Trainium2, the second-generation chip, became generally available through AWS in late 2024 and was marketed heavily at customers running large language model training and inference. Its performance-per-dollar, according to AWS’s own benchmarks, is roughly thirty to forty per cent better than AWS’s GPU-based P5 and P5en instances on comparable workloads, with sustained workloads showing roughly fifty-four per cent lower cost per token for GPT-class models. The chips run on TSMC’s 5-nanometre process, carry 96 gigabytes of HBM3 per chip, and deliver 1.3 petaflops of dense FP8 compute or 5.2 petaflops of sparse FP8 compute per chip.
Trainium2 systems are typically deployed in Trn2 UltraServers, each of which carries 64 chips connected via Amazon’s proprietary NeuronLink interconnect and delivers 83.2 peak petaflops of compute. The largest single deployment of Trainium2 is Project Rainier, an AWS EC2 UltraCluster built specifically for Anthropic. AWS declared Rainier fully operational on 29 October 2025. The cluster carries nearly 500,000 Trainium2 chips across several United States data centres, anchored by an approximately eleven-billion-dollar campus near New Carlisle in Indiana on a 1,200-acre site, with additional facilities in Mississippi and elsewhere. By the time of the April 2026 announcement, Anthropic said it was running on more than a million Trainium2 chips.
The chip’s successor, Trainium3, became available in December 2025. It is AWS’s first three-nanometre AI chip, carries 144 gigabytes of HBM3e per chip, and delivers 2.52 petaflops of FP8 compute per chip, roughly twice Trainium2’s dense throughput at forty per cent better energy efficiency. A Trainium3 UltraServer carries 144 chips in a single domain and delivers 362 petaflops of FP8 compute. AWS has said that Trainium3 customers have cut training and inference costs by up to fifty per cent relative to comparable GPU systems, and that Anthropic is among them.
The April 2026 expansion of the Anthropic deal committed Amazon to invest up to twenty-five billion dollars more in Anthropic and to deploy up to five gigawatts of new Trainium capacity across Trainium2, Trainium3, and a forthcoming Trainium4. Anthropic in turn pledged to spend more than one hundred billion dollars on AWS over the following decade. The deal sits alongside Anthropic’s parallel agreement with Google for TPUs, its roughly forty-five-billion-dollar agreement with Nscale for NVIDIA Vera Rubin systems, and its CoreWeave, SpaceX Colossus, Fluidstack, and Akamai contracts. Anthropic is now simultaneously one of the largest customers of three different accelerator families, and is on record saying that matching workloads to the right silicon is part of its competitive advantage.
Microsoft’s Maia – the cautionary tale
Microsoft’s custom-silicon programme is the most complicated of the four, and the one that has had the most trouble. The company unveiled its first-generation accelerator, Maia 100, at Ignite in November 2023. Maia 100 is a 105-billion-transistor chip manufactured on TSMC’s 5-nanometre process with CoWoS-S packaging, roughly 820 square millimetres of silicon paired with 64 gigabytes of HBM2E memory at around 1.8 terabytes per second of bandwidth, with peak dense BF16 tensor performance of around 800 teraflops and a designed-for 700-watt TDP typically provisioned at 500 watts in rack. The chip was meant to handle the largest of Microsoft’s internal AI workloads: Microsoft Copilot, the Azure OpenAI Service, GitHub Copilot, Bing’s generative features, and OpenAI inference running on Microsoft’s behalf.
It did not work out that way. Multiple outlets, including The Information and Tom’s Hardware, reported in 2024 and 2025 that Maia 100 ended up being used primarily for internal staff training and validation rather than as a production accelerator for OpenAI’s flagship models. Microsoft never released a Maia virtual machine SKU for external customers. The follow-on inference part, originally codenamed Braga, was delayed into 2026 and emerged as Maia 200.
Maia 200, unveiled in January 2026, is built on TSMC’s 3-nanometre process with 216 gigabytes of memory. It runs OpenAI’s GPT-5.2 inference, Microsoft Foundry, Microsoft 365 Copilot, and the work of Microsoft’s Superintelligence team on synthetic data and reinforcement learning. Production deployments have begun in Microsoft’s US Central region near Des Moines, Iowa, and at the US West 3 region near Phoenix, Arizona, with additional regions in Italy, Australia, and South Korea scheduled to follow.
The reason Microsoft’s custom silicon has been harder to scale than Google’s or Amazon’s is not that the engineering is bad. It is that Microsoft’s relationship with OpenAI gave it a uniquely captive workload, and the workload itself runs at the very frontier of capability, where model quality matters far more than chip cost. OpenAI’s flagship models are still trained primarily on Nvidia systems in Azure data centres, and Microsoft’s compute-spend on Nvidia dwarfs its custom-silicon investment. Maia’s commercial role, as a result, has converged on inference rather than frontier training. Custom silicon for Microsoft looks more like a way to capture margin on commodity inference than to escape Nvidia.
Meta’s MTIA – the silent ASIC
Meta’s strategy is the most unusual of the four. The company has been designing inference accelerators since 2020 and has shipped roughly two MTIA generations every two years, with six generations either shipping or in development by 2026. The first-generation MTIA 100 was a small chip designed for ranking and recommendation inference. The second-generation MTIA 200 (also called MTIA 2i) was disclosed in 2024 and is the chip that scaled. Meta has hundreds of thousands of MTIA 200 chips deployed across its data centres, primarily serving its ads workloads, with a rack-scale system of seventy-two accelerators delivering around fifty petaflops of INT8 inference and a roughly forty-four per cent TCO reduction versus GPU inference for production recommendation models. Meta has published two ISCA papers on the architecture and is candid about the design constraints: the chip has outsized SRAM capacity for low-batch utilisation, doubled memory capacity to 128 gigabytes of DDR5, runs at 1.35 gigahertz and ninety watts, and uses PCI Express 5.0 for host connectivity.
What is new in 2025 and 2026 is that MTIA is no longer an ads-only chip. Meta’s MTIA 300 is a step towards general AI workloads. MTIA 400 is the first MTIA part designed specifically for generative AI training and inference, with a 72-accelerator scale-up domain competitive with leading commercial products, and Meta says it has finished lab testing and is on the path to deployment in 2026. MTIA 450, scheduled for mass deployment in early 2027, is optimised specifically for generative AI inference. MTIA 500, scheduled for 2027, increases HBM bandwidth by an additional fifty per cent over MTIA 450 and adds further low-precision data-format support.
The MTIA roadmap is also where Broadcom enters the story. In August 2024 Broadcom and Meta announced an extended partnership under which Broadcom will co-design and deploy MTIA chips for Meta through 2029, with the first phase alone exceeding one gigawatt of capacity and the full programme representing a sustained multi-gigawatt rollout. The partnership is also where Meta’s interest in alternative accelerators is most explicit: Broadcom is simultaneously the design partner for Google’s TPUs and is now the design partner for Meta’s MTIA. When Meta needed additional general AI compute in 2026, the company entered advanced talks with Google to deploy on-prem TPU pods starting in 2027, a further sign that Meta sees TPU as a complement to its own MTIA rather than a substitute for it.
Meta also continues to spend very heavily on Nvidia. The company reportedly spent roughly fifteen billion dollars on Nvidia GPUs alone between 2017 and 2024. The MTIA programme is a way of reducing that dependency for a specific class of workload, not of eliminating it. The advertising business is the workload MTIA was built for; the generative AI business is the workload Nvidia still anchors.
The hidden designers – Broadcom and Marvell
Most of the hyperscaler chips described above are not designed by the hyperscalers alone. They are co-designed with two American semiconductor companies whose names are not often in the headlines but whose fingerprints are on nearly every major accelerator programme of the last decade.
Broadcom is the larger and more visible of the two. It co-designed every recent generation of Google’s TPU through a long-running partnership that has now been renewed into the 2030s. It is Meta’s partner on MTIA, with the multi-gigawatt agreement announced in August 2024. It does custom ASIC work for other large customers as well, including several of the Chinese hyperscalers. The bulk of Broadcom’s AI-related revenue, on the order of tens of billions of dollars per year by 2026, comes from co-designing chips that ship under other people’s brand names.
Marvell is the smaller and more diversified of the two. It designs custom silicon for cloud platforms, including hyperscaler-specific XPUs, with an IP portfolio spanning high-speed SerDes, die-to-die interconnects, silicon photonics, advanced packaging, custom HBM designs, and compute-fabric interfaces including PCIe Gen 7. Marvell’s design services let customers integrate their own logic with Marvell’s IP at TSMC’s 3-nanometre node and beyond. The company has long-standing custom-silicon relationships across the industry, including work for Amazon’s Trainium family and for several non-hyperscaler customers.
In May 2025 Nvidia announced NVLink Fusion, a silicon-and-software programme that lets third-party accelerators integrate with Nvidia’s rack-scale systems at up to 1.8 terabytes per second of bidirectional bandwidth. The first partners were MediaTek, Marvell, Alchip Technologies, Astera Labs, Synopsys, and Cadence. Marvell in particular became a strategic partner for Nvidia: in September 2025 Nvidia invested two billion dollars in Marvell as part of a wider partnership to deliver custom XPUs and scale-up networking for AI factories. Every NVLink Fusion platform must include at least one Nvidia product to function, which means Marvell-designed accelerators still generate revenue for Nvidia even when they are not Nvidia chips.
The custom-silicon war is therefore not just a war between hyperscalers and Nvidia. It is also a war between different ways of being a custom-silicon company. Broadcom and Marvell both sell design services to hyperscalers. They are also now competing with Nvidia’s own design-and-fabric programme via NVLink Fusion. The contract designers will, in many cases, determine who wins.
Nvidia’s counter-strike
Nvidia’s response to the custom-silicon wave is more sophisticated than the simple “buy more GPUs” story suggests. The company has spent the last two years building three layers of defence.
The first is NVLink Fusion. By licensing its interconnect and rack-scale architecture to third-party accelerator designers, Nvidia ensures that even chips it does not make can still be deployed inside Nvidia’s rack systems, on Nvidia’s networking, and managed by Nvidia’s software. From a customer perspective, a Marvell-designed XPU running inside an NVLink Fusion rack looks a lot like an Nvidia system. The hyperscaler that designs its own accelerator but buys into NVLink Fusion is still paying Nvidia for the surrounding fabric.
The second is the Vera Rubin generation. Vera Rubin, due in volume through 2026 and 2027, extends Blackwell’s lead on raw compute, memory bandwidth, and rack-scale integration. The Rubin Ultra generation, which Nvidia has previewed, pushes the architecture further. Vera Rubin is also where Nvidia’s moat widens for the largest workloads: training a single frontier model in 2027 is expected to require on the order of two gigawatts of continuous compute, and Vera Rubin’s per-rack and per-cluster integration advantages are most visible at exactly that scale.
The third is the open-vs-proprietary interconnect battle. NVLink Fusion is proprietary. In response, AMD, Intel, Broadcom, and several other companies formed the UALink consortium to push an open standard for rack-scale accelerator interconnects. UALink promises lower cost and more interoperability, but it is several years behind NVLink in deployment and lacks Nvidia’s installed-base advantage. The contest between NVLink Fusion and UALink will shape how the next generation of accelerators talk to each other inside a rack, and therefore how much value flows back to Nvidia.
The $2 billion investment in Marvell is the most strategically interesting of these moves. It pulls Marvell, one of the most important hyperscaler-chip design partners, into Nvidia’s interconnect ecosystem. It does not stop Marvell from designing for hyperscalers, but it ensures that the chips Marvell designs for those hyperscalers will integrate more cleanly with Nvidia systems than with UALink or any alternative. The investment is, in effect, a quiet way of colonising the custom-silicon ecosystem from the inside.
The real bottleneck
There is one more layer of the story that matters more than any of the chip-design battles, and that is the layer that nobody can design around: the physical infrastructure of advanced packaging and high-bandwidth memory.
Every modern AI accelerator is built from at least two kinds of silicon. The first is a logic die, manufactured on TSMC’s most advanced process nodes, which does the actual matrix-multiplication work. The second is one or more stacks of HBM memory, manufactured by Micron, Samsung, or SK Hynix, which feed the logic die with weights and activations at very high bandwidth. The two are bonded together using advanced packaging, of which the dominant technique is TSMC’s Chip-on-Wafer-on-Substrate, or CoWoS. Without CoWoS, an H100, a Trillium, a Trainium2, or a Vera Rubin does not exist as a working chip.
CoWoS capacity is the binding constraint on the entire AI chip industry in 2026. TSMC ramps CoWoS wafer output from roughly 75,000 to 80,000 wafers per month at the start of 2026 toward 120,000 to 130,000 by the end of the year. Total demand for 2026 is estimated at roughly one million wafers, up from about 670,000 in 2025 and 370,000 in 2024. Demand has tripled in two years and is still ahead of supply. Lead times for the most advanced CoWoS variants, including CoWoS-L used by Blackwell and Vera Rubin, are reported at fifty-two to seventy-eight weeks. Nvidia holds an estimated sixty per cent of the total capacity, with the top three customers, Nvidia, Broadcom, and AMD, holding more than eighty-five per cent. TSMC’s CEO said in mid-2026 that packaging capacity is now limiting his customers’ growth, the closest thing to a rationing statement the company has ever made.
HBM is the second bottleneck, and it is expected to remain binding through 2027. All three major suppliers are effectively sold out across 2026. HBM4, the next generation, is in qualification now and is expected to ship at scale in 2027, but the qualification cycle is unforgiving and demand is running well ahead of supply. ABF substrates, the organic interposers used inside CoWoS packages, are the third constraint: a single Japanese supplier holds more than ninety-five per cent of global ABF capacity, and analysts expect the supply gap to widen from ten per cent in the second half of 2026 to roughly forty-two per cent by 2028.
The implication is straightforward. The custom-silicon war is being decided, in practice, by who has secured CoWoS wafer allocations and HBM purchase contracts. Hyperscalers that have done so, Google most prominently, can ship at scale. Hyperscalers that have not, including several Chinese programmes and many smaller custom-silicon programmes, cannot. Nvidia’s dominance of CoWoS is not a marketing advantage. It is a physical one, and it is the reason why the GPU monopoly has so far bent but not broken.
## What it all means
The custom-silicon war of 2026 is real, and it is changing the structure of the AI industry. Google’s TPUs now train Gemini and serve a substantial fraction of Anthropic’s Claude traffic. Amazon’s Trainium chips now train and serve Anthropic’s Claude at a scale no previous non-Nvidia accelerator has reached. Meta’s MTIA programme has crossed from ads-specific to general AI workloads, with the most aggressive scaling of any of the hyperscaler programmes and a multi-gigawatt partnership with Broadcom through 2029. Microsoft has a working custom-silicon programme for inference, even if it remains dependent on Nvidia for the heaviest frontier training.
The economic story underneath is straightforward. Hyperscalers are no longer willing to pay full Nvidia margins on every chip they buy, especially for inference workloads where the workload fit is poor. They are willing to spend billions on alternative silicon and to absorb years of engineering pain to do so. The deals struck in 2025 and 2026, Anthropic’s trillion-dollar compute portfolio, Google’s TPU and Broadcom partnership, Amazon’s Project Rainier, Meta’s MTIA roadmap, represent the largest sustained industrial commitment to non-Nvidia silicon in the history of the industry.
Nvidia is not going anywhere. Its share of frontier training remains dominant, its rack-scale systems remain the default for the largest jobs, and its grip on CoWoS capacity and the NVLink ecosystem ensures that even non-Nvidia accelerators tend to feed into Nvidia’s networking stack. The custom-silicon war has not ended Nvidia’s dominance. What it has done is end the assumption that Nvidia’s dominance is permanent. By 2027 the leading frontier labs will be running roughly half their compute on accelerators they did not buy from Nvidia, and that fraction will rise through the rest of the decade. The GPU monopoly did not collapse. It is being surrounded, one workload at a time.
