Optical Interconnects Break the AI Power Wall

By Nekud October 16, 2026 16 min read

The question of whether optical interconnects can break the AI power wall by 2028 became, in the AI Infra Summit 2026 panel discussions, the most consequential open question in the AI infrastructure industry’s near-term technology planning. The question was being asked, by late 2026, because the AI compute buildout’s increasing power density is pushing the conventional copper-based interconnect architecture to its physical limits. The conventional copper interconnect, which has been the principal interconnect technology for both rack-scale and superpod-scale AI compute architecture since the early 2020s, is running out of headroom. The copper interconnect is bandwidth-limited at the highest data rates, power-limited at the highest densities, and reach-limited at the highest speeds. The optical interconnect, which had been a niche technology for the highest-end long-haul fibre connections, is, in late 2026, becoming the principal interconnect technology for the rack-scale and superpod-scale AI compute architecture that the AI compute workload requires.

The question of whether optical interconnects can break the AI power wall by 2028 is being asked with some urgency, because the AI compute workload’s power density is increasing faster than the copper interconnect’s ability to handle the resulting bandwidth and power requirements. A 1 gigawatt AI data-centre campus is, on the late-2026 silicon projections, going to be served by tens of thousands of AI compute accelerators, with each accelerator running at roughly 1 kilowatt of power consumption. The accelerators are connected to each other through a network that has to handle substantial bandwidth at substantial power efficiency, and the network has to do so over distances of metres to tens of metres within the rack and superpod. The copper interconnect that has been the dominant technology for the rack-scale and superpod-scale networks of the early 2020s is, on the published engineering analyses, hitting its practical limits at the bandwidths and the power densities that the late-2020s AI compute workload requires.

The optical interconnect has been, since the late 1990s, a niche technology for the highest-end long-haul fibre connections and for the highest-end data-centre inter-rack fibre connections. The optical interconnect’s advantages are its bandwidth (which can scale to terabits per second per fibre), its reach (which can extend to kilometres without amplification), and its power efficiency (which is substantially better than copper at high data rates). The optical interconnect’s disadvantages are its cost (which has historically been substantially higher than copper’s), its packaging complexity (which requires the integration of lasers, modulators, and detectors into the silicon), and its system-level design complexity (which requires the integration of the optical interconnect with the rack-level and superpod-level architecture). The optical interconnect’s cost and complexity have, historically, been the binding constraints on the technology’s adoption. The cost and complexity constraints are being substantially reduced by the late 2020s, with the result that the optical interconnect is becoming the principal interconnect technology for the AI compute workload.

This essay traces the optical interconnect’s emergence as the principal interconnect technology for the AI compute workload through three threads. The first is the technology thread: what the optical interconnect architecture looks like, what the principal technological choices in the optical interconnect are, and what the principal suppliers of the optical interconnect are. The second is the adoption thread: how the optical interconnect is being adopted in the rack-scale and superpod-scale architecture of the principal AI compute customers, and how the adoption is being driven by the AI compute workload’s needs. The third is the strategic thread: what the optical interconnect implies for the broader AI compute industry, what the implications are for the silicon photonics industry that the optical interconnect is built on, and what the implications are for the AI compute industry’s longer-term architecture. The thesis the essay develops is the following. Optical interconnects are going to break the AI power wall by 2028, and the optical interconnect’s emergence as the principal interconnect technology for the AI compute workload is going to be one of the most consequential architectural changes in the AI infrastructure industry in the late 2020s.

What optical interconnects are and how they work

An optical interconnect, in the AI compute context, is a system that converts electrical signals from an AI compute accelerator into optical signals, transmits those optical signals through a fibre or through a free-space optical path, and converts the optical signals back into electrical signals at the destination. The conversion is done by an optical transmitter (typically a laser or a modulator driven by a laser) at the source end and by an optical receiver (typically a photodetector) at the destination end. The optical interconnect can be implemented at several different points in the system: it can be implemented at the chip-to-chip level (converting signals between chips on a circuit board), at the board-to-board level (converting signals between boards in a rack), at the rack-to-rack level (converting signals between racks in a data centre), or at the campus-to-campus level (converting signals between data centres across long-haul fibre).

The optical interconnect’s principal advantage over the copper interconnect is its ability to handle much higher data rates at much longer reaches than copper. A copper interconnect can typically handle data rates of up to roughly 100 gigabits per second per channel, and the reach of a copper interconnect at the highest data rates is limited to roughly a metre. An optical interconnect, by contrast, can handle data rates of up to several hundred gigabits per second per channel, and the reach of an optical interconnect can extend from a few centimetres (for chip-level optical interconnect) to many kilometres (for long-haul fibre optical interconnect). The higher data rate and the longer reach come from the physical properties of the optical signal: the optical signal is not subject to the same resistance, capacitance, and crosstalk limits that the electrical signal is, and the optical signal can be carried through the optical fibre at very low loss over very long distances.

The optical interconnect’s principal disadvantage, historically, has been its cost. The optical interconnect requires, in addition to the optical fibre itself, a laser (or a modulator driven by a separate laser), a photodetector, and the electronic driver and transimpedance amplifier chips that interface the optical interconnect with the conventional CMOS logic. The lasers, modulators, and photodetectors have, in the past, been fabricated using compound-semiconductor processes (most commonly indium phosphide) that are more expensive than the silicon processes used for the CMOS logic. The packaging of the optical interconnect, which requires the laser to be precisely aligned with the optical fibre, has also been more expensive than the packaging of the copper interconnect. The cumulative cost of the optical interconnect has, historically, been substantially higher than the cost of the copper interconnect, and the cost has been the binding constraint on the optical interconnect’s adoption in the rack-scale and superpod-scale architecture.

The cost of the optical interconnect is being substantially reduced by the silicon-photonics technology that is being deployed in the late 2020s. Silicon photonics is the integration of the laser, the modulator, and the photodetector onto a silicon die that is fabricated using a conventional CMOS-compatible process. The silicon-photonics integration allows the optical interconnect’s components to be fabricated at substantially lower cost than the conventional compound-semiconductor fabrication, and the silicon-photonics integration also allows the optical interconnect’s components to be packaged more easily than the conventional compound-semiconductor packaging. The cumulative cost reduction from the silicon-photonics integration is substantial, with the cost of the optical interconnect being reduced, on the published engineering analyses, by a factor of roughly 5 to 10 over the past several years.

How optical interconnects are being adopted in the AI compute architecture

The optical interconnect is being adopted in the AI compute architecture at three principal levels: the chip-to-chip level, the rack-scale level, and the superpod-scale level. The chip-to-chip optical interconnect is the most architecturally distinctive of the three, and it is the level at which the optical interconnect is being adopted most aggressively. The chip-to-chip optical interconnect uses an optical transmitter and an optical receiver that are integrated into the AI compute accelerator chip package, with the optical signal carried between the chips on a short-distance optical link on the circuit board. The chip-to-chip optical interconnect is, on the engineering analyses, capable of substantially higher bandwidth than the copper-based chip-to-chip interconnect, and the chip-to-chip optical interconnect is also substantially more power-efficient than the copper-based chip-to-chip interconnect at the highest data rates.

The rack-scale optical interconnect is the second level at which the optical interconnect is being adopted. The rack-scale optical interconnect uses an optical transmitter and an optical receiver that are integrated into the rack-mounted optical transceiver, with the optical signal carried between the rack-mounted devices on a rack-scale optical fibre network. The rack-scale optical interconnect is, on the engineering analyses, capable of substantially higher bandwidth than the copper-based rack-scale interconnect, and the rack-scale optical interconnect is also substantially more power-efficient than the copper-based rack-scale interconnect at the highest data rates. The rack-scale optical interconnect is being adopted by several of the largest AI compute customers, with the NVIDIA Spectrum-6 Ethernet switch and the AMD Helion specification both including substantial rack-scale optical interconnect components.

The superpod-scale optical interconnect is the third level at which the optical interconnect is being adopted. The superpod-scale optical interconnect uses an optical transmitter and an optical receiver that are integrated into the superpod-scale optical switch, with the optical signal carried between the racks on a superpod-scale optical fibre network. The superpod-scale optical interconnect is, on the engineering analyses, capable of substantially higher bandwidth than the copper-based superpod-scale interconnect, and the superpod-scale optical interconnect is also substantially more reach-efficient than the copper-based superpod-scale interconnect at the highest data rates. The superpod-scale optical interconnect is being adopted by several of the largest AI compute customers, with the Microsoft Maia 300 superpod’s two-tier Ethernet-based scale-up network using the superpod-scale optical interconnect as its principal interconnect architecture.

The timing of the optical interconnect’s adoption at each of the three levels is being driven by the AI compute workload’s needs at the level in question. The chip-to-chip optical interconnect is being adopted first, with the adoption being driven by the AI compute workload’s need for substantially higher bandwidth between the AI compute accelerators and the HBM memory at the chip level. The rack-scale optical interconnect is being adopted second, with the adoption being driven by the AI compute workload’s need for substantially higher bandwidth between the AI compute accelerators at the rack level. The superpod-scale optical interconnect is being adopted third, with the adoption being driven by the AI compute workload’s need for substantially higher bandwidth between the racks at the superpod level. The staggered timing of the adoption reflects the fact that the AI compute workload’s needs are most acute at the chip level, less acute at the rack level, and least acute at the superpod level.

The silicon photonics industry that the optical interconnect is built on

The optical interconnect that is being adopted in the AI compute architecture is being built on a silicon-photonics industry that has been growing rapidly through the late 2020s. The silicon-photonics industry is, in 2026, one of the fastest-growing segments of the semiconductor industry, with the silicon-photonics industry’s revenue having grown at well over 30 percent per year through 2025 and 2026 and with the silicon-photonics industry’s revenue being projected, on several research-firm forecasts, to exceed 30 billion dollars by 2030. The silicon-photonics industry’s growth is being driven principally by the AI compute workload’s need for the optical interconnect, and the silicon-photonics industry is, in turn, becoming one of the most strategically important segments of the semiconductor industry.

The principal silicon-photonics suppliers are a mix of established semiconductor companies and dedicated silicon-photonics startups. Intel has been one of the largest silicon-photonics suppliers for several years, with its silicon-photonics products being integrated into several of the largest AI compute architectures. Broadcom has been another large silicon-photonics supplier, with its silicon-photonics products being integrated into the Google TPU family and into several of the other hyperscaler custom-silicon programs. Cisco, through its acquisition of Acacia Communications, has been a substantial silicon-photonics supplier for the long-haul fibre market. Marvell has been a substantial silicon-photonics supplier for the data-centre interconnect market. The dedicated silicon-photonics startups — including Ayar Labs, Lightmatter, Lightelligence, Celestial AI, and several others — have been pushing the technology’s leading edge and have been raising substantial venture capital to support their growth.

The Lightelligence company that we discussed in the photonic-compute essay for huaxia.click is also a substantial player in the optical interconnect market. Lightelligence has, in addition to its photonic-compute accelerators, developed substantial optical interconnect products, and the company is one of the leading suppliers of the chip-to-chip optical interconnect products that are being adopted in the AI compute architecture. The Lightelligence’s diversified portfolio is a useful illustration of the silicon-photonics industry’s convergence: the same silicon-photonics technology that supports the photonic-compute accelerator also supports the optical interconnect, and the companies that have invested in the silicon-photonics technology have been able to address multiple markets with the same underlying technology.

The silicon-photonics industry’s growth is being supported by substantial new investment in the silicon-photonics fabrication capacity. Several of the principal foundries — TSMC, GlobalFoundries, and Intel — have substantially expanded their silicon-photonics fabrication capacity through 2025 and 2026. The new fabrication capacity is being driven by the optical interconnect’s demand for substantial volumes of silicon-photonics products, and the new fabrication capacity is, in turn, allowing the silicon-photonics products to be supplied at a price that the AI compute customers can afford. The silicon-photonics fabrication capacity is, in late 2026, one of the principal supply-side constraints on the AI compute buildout, with several of the AI compute customers reporting that the silicon-photonics products are being delivered on longer lead times than the AI compute accelerators themselves.

The strategic implications of the optical interconnect

The optical interconnect’s emergence as the principal interconnect technology for the AI compute workload has substantial strategic implications for the broader AI infrastructure industry. The first strategic implication is that the optical interconnect is, by late 2026, becoming one of the largest single categories of capital expenditure in the AI compute buildout. The optical interconnect’s share of the AI compute rack’s bill-of-materials is, on the late-2026 silicon projections, going to be roughly 10 to 15 percent by 2030, with the share having risen from roughly 2 to 5 percent in the early 2020s. The optical interconnect’s growing share of the bill-of-materials is making the optical interconnect a substantial single category of capital expenditure, and the optical interconnect is, in turn, becoming one of the most strategically important segments of the AI compute industry.

The second strategic implication is that the optical interconnect is reshaping the competitive landscape of the data-centre networking market. The data-centre networking market has, since the early 2020s, been dominated by a small number of suppliers (principally Cisco, Arista Networks, Juniper, and NVIDIA through its Mellanox acquisition). The optical interconnect’s emergence as the principal interconnect technology is allowing a substantial number of new entrants into the data-centre networking market, with the silicon-photonics startups and the established semiconductor companies (notably Intel and Broadcom) all entering the market with substantial new products. The optical interconnect is, in turn, reshaping the data-centre networking market’s competitive dynamics, with the result that the data-centre networking market is going to be substantially more competitive in the late 2020s than it was in the early 2020s.

The third strategic implication is that the optical interconnect is reshaping the competitive landscape of the broader semiconductor industry. The silicon-photonics industry is, by late 2026, one of the fastest-growing segments of the semiconductor industry, with the silicon-photonics industry’s growth being substantially faster than the broader semiconductor industry’s growth. The silicon-photonics industry’s growth is, in turn, allowing the silicon-photonics suppliers to take a larger share of the broader semiconductor industry’s revenue, and the silicon-photonics suppliers are becoming some of the most strategically important companies in the semiconductor industry. The Intel, Broadcom, and Marvell silicon-photonics businesses are all, on the late-2026 revenue figures, among the fastest-growing single segments of those companies’ revenue.

The fourth strategic implication is that the optical interconnect is going to be the principal determinant of how quickly the AI compute buildout can proceed past the power-wall constraint. The AI compute workload’s power consumption is, by late 2026, becoming the binding constraint on the AI compute buildout’s pace, and the optical interconnect’s ability to substantially reduce the per-bit power consumption of the AI compute interconnect is, in turn, going to substantially relieve the power-wall constraint. The MIT researcher Vijay Gadepally’s estimate, reported in the AI Daily 2026-10-12 roundup, that some 50 to 100 MW data centres could reclaim 10 to 20 percent of their power through better controls is, in substantial part, a reflection of the optical interconnect’s potential contribution to the per-bit power efficiency of the data-centre interconnect. The optical interconnect’s contribution to the power efficiency is, in turn, going to be a substantial enabler of the AI compute buildout’s continued growth.

The longer-term trajectory of the optical interconnect

The optical interconnect’s trajectory over the longer term is going to be one of the most consequential technology-trajectories in the AI infrastructure industry of the late 2020s and the early 2030s. The principal longer-term trajectory is the move from the chip-to-chip and rack-scale optical interconnect that is being deployed in the late 2020s to the wafer-scale and package-scale optical interconnect that is going to be deployed in the early 2030s. The wafer-scale and package-scale optical interconnect is, on the engineering analyses, capable of even higher bandwidth and even lower power consumption than the chip-to-chip and rack-scale optical interconnect that is being deployed in the late 2020s, and the wafer-scale and package-scale optical interconnect is being developed by several of the principal silicon-photonics companies.

The second principal longer-term trajectory is the move from the silicon-photonics technology that is being deployed in the late 2020s to the heterogeneous-integration silicon-photonics technology that is going to be deployed in the early 2030s. The heterogeneous-integration silicon-photonics technology combines the silicon photonics with compound-semiconductor lasers and photodetectors in a single package, allowing the optical interconnect’s components to be integrated into the AI compute accelerator’s package at substantially lower cost and substantially higher density than the discrete-component silicon photonics that is being deployed in the late 2020s. The heterogeneous-integration silicon-photonics technology is being developed by several of the principal silicon-photonics companies and is expected to be commercially deployed in the early 2030s.

The third principal longer-term trajectory is the move from the optical interconnect’s principal role as a data-centre interconnect technology to its principal role as a chip-level interconnect technology. The chip-level optical interconnect is, on the engineering analyses, capable of substantially higher bandwidth and substantially lower power consumption than the chip-level copper interconnect, and the chip-level optical interconnect is being developed by several of the principal silicon-photonics companies. The chip-level optical interconnect is, however, substantially more difficult to deploy than the rack-scale and superpod-scale optical interconnect, with the chip-level optical interconnect requiring substantial new packaging technology and substantial new manufacturing infrastructure.

The optical interconnect is, in summary, going to break the AI power wall by 2028, and the optical interconnect’s emergence as the principal interconnect technology for the AI compute workload is going to be one of the most consequential architectural changes in the AI infrastructure industry in the late 2020s. The optical interconnect is being deployed at three levels — the chip-to-chip level, the rack-scale level, and the superpod-scale level — and the deployment is being driven by the AI compute workload’s need for substantially higher bandwidth and substantially lower power consumption at each of the three levels. The optical interconnect’s emergence is reshaping the competitive landscape of the data-centre networking market, the competitive landscape of the broader semiconductor industry, and the principal determinant of how quickly the AI compute buildout can proceed past the power-wall constraint. The optical interconnect’s longer-term trajectory is, in many respects, the trajectory of the AI compute industry itself.